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arm_interrupt_controllers [2024/06/02 22:40]
cnigri Incorporacion de registro de control de la interfaz con el CPU |
arm_interrupt_controllers [2024/06/03 20:16] (actual)
cnigri Fix Incorporacion de registro de control de la interfaz con el CPU |
| #define ICCIAR *((uint32_t *) GIC0_CPU_BASE + 0x0C) //Interrupt Acknowledge | #define ICCIAR *((uint32_t *) GIC0_CPU_BASE + 0x0C) //Interrupt Acknowledge |
| #define ICCEOIR *((uint32_t *) GIC0_CPU_BASE + 0x10) //End of Interrupt Register | #define ICCEOIR *((uint32_t *) GIC0_CPU_BASE + 0x10) //End of Interrupt Register |
| #define ICDDCR *((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0x000) //Distributor Control Register | |
| #define ICDICTR *((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0x004) //Interrupt Controller Type Register | |
| #define ICDISER(n) *(((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0x100) + n) //Interrupt n Set-Enable Registers | |
| #define ICDICER(n) *(((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0x180) + n) //Interrupt Clear-Enable Registers | |
| #define ICDIPR(n) *(((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0x400) + n) //Interrupt Priority Registers | |
| #define ICDIPTR(n) *(((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0x800) + n) //Interrupt Processor Targets Registers | |
| #define ICDICFR(n) *(((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0xC00) + n) //Interrupt Configuration Registers | |
| #define ICDDCR *((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0x000) //Distributor Control Register | #define ICDDCR *((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0x000) //Distributor Control Register |
| #define ICDICTR *((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0x004) //Interrupt Controller Type Register | #define ICDICTR *((uint32_t *) GIC0_DISTRIBUTOR_BASE + 0x004) //Interrupt Controller Type Register |
